Image sensor devices contained in ICs are made up of arrays of pixels. Each pixel comprises a plurality of transistors that function as gates, signal control lines that control the operations of the pixel through switching of the gates, and a photodiode that receives light and produces electrical signals in response to the received light. FIG. 1 illustrates a schematic diagram of a known pixel 2 that has four transistors 3-6, reset (RST), Transfer (TX) and Row control lines 7, 8 and 9, and a photodiode 11. This pixel 2 is a four-transistor (4-T) buried gated photodiode device commonly referred to as a 4-T pinned photodiode pixel. External to the pixel 2 is an analog readout column line 12, a current source 13, a reset sampling switch 14 controlled by reset sampling signal S1, a capacitor C 15, a video sampling switch 16 controlled by video sampling signal S2, and a capacitor C 17. The reset sampling switch 14 connects and disconnects capacitor C 15 to and from the readout column line 12. Likewise, the video sampling switch 16 connects and disconnects capacitor C 17 to and from the readout column line 12.
FIG. 2 illustrates a timing diagram that demonstrates the operations of the pixel 2 during sampling of the reset and video sample values. To sample the pixel 2, the Row control signal 9 is asserted high. When the reset sampling signal S1 goes high, switch 14 is closed connecting the capacitor C 15 to the analog readout column line 12. The RST control signal 7 then goes high. The TX control signal 8 and the video sampling signal S2 are both low at this time. When the RST control signal 7 is high, the RST transistor 3 is on and the floating diffusion (FD) node 18 is connected to the power supply, VDD, which turns on the source follower (SF) transistor 4 and causes a buffered voltage corresponding to the voltage on the FD node 18 to be driven onto the analog readout column line 12. When the reset sampling signal S1 goes low, switch S1 14 opens and stores the value of the analog readout column line 12 on the reset storage capacitor C 15. This value is the reset sampling value of the pixel 2.
After reset sampling signal S1 goes low, the video sampling signal S2 goes high. When the video sampling signal S2 goes high, switch 16 is closed connecting the capacitor C 17 to the analog readout column line 12. The TX control signal 8 then goes high. The RST control signal 7 and the reset sampling signal S1 are both low at this time. When the TX control signal 8 goes high, the TX transistor 5 is turned on, connecting the photodiode 11 to the FD node 18. Charge that had been previously integrated on the photodiode 11 due to light is transferred to the FD node 18 at this time. The SF transistor 4 is turned on. This causes the video sampling value, which corresponds to the value of the voltage on the FD node 18 at this time, to be driven onto the analog readout column line 12. When video sampling signal S2 goes low, switch S2 16 opens and stores the value of the analog readout column line 12 on the video storage capacitor C17. This value is the video sampling value of the pixel 2.
On the falling edge of the reset sampling signal S1 (indicated by dashed line 19), the reset sampling value stored on capacitor C 15 is sampled by sampling circuitry (not shown) and converted from an analog reset sampling value to a digital reset sampling value. Likewise, on the falling edge of the video sampling signal S2 (indicated by dashed line 21), the video sampling value stored on capacitor C 17 is sampled by sampling circuitry (not shown) and converted from an analog video sampling value to a digital video sampling value. The difference between the digital reset and video sampling values is then obtained, and this difference value corresponds to the pixel sample value.
In the image sensor industry, efforts are continuously being made to reduce the amount of area consumed by the transistors, signal control lines and readout circuitry of the pixels. At the same time, efforts are also being made to increase the photodiode area. As the area of the SF transistor in the pixel decreases, temporal fluctuations in the threshold voltage of the SF transistor increase. Because of the temporal variation in the threshold voltage of the SF transistor, the threshold voltage may not be the same when the reset sampling value and the video sampling value are taken. The temporal variation in threshold voltage of each pixel results in random noise in the reset and video sampling values, which, of course, is undesirable. This type of noise is sometimes referred to in the image sensor industry as random telegraph noise. In addition, as the transistors are made increasingly smaller, the differences between the threshold voltages that can exist when the reset sampling value and the video sampling value are taken also increase, which increases the amount of telegraph noise contained in the reset and video sampling values.
Currently, the only practical solution for reducing random telegraph noise is to increase the size of the SF transistor. Increasing the size of the SF transistor, however, increases the overall size of the pixel, which is undesirable. In addition, increasing the size of the SF transistor also decreases the fill factor (i.e., the amount of area that is available for implementing the photodiode), which also is undesirable.
Accordingly, a need exists for a way to eliminate or reduce random telegraph noise in image sensor devices. A need also exists for a way to eliminate or reduce random telegraph noise in image sensor devices without having to increase the size of the SF transistor and without having to reduce the pixel fill factor.